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acpl-k34t automotive 2.5 a peak high output current mosfet gate drive optocoupler with rail-to-rail output voltage in stretched so8 data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product description avago's 2.5 amp automotive r 2 coupler gate drive op - tocoupler contains an algaas led, which is optically cou - pled to an integrated circuit with a power output stage. the acpl-k34t features fast propagation delay and tight timing skew, is ideally designed for driving power mos - fets used in ac-dc and dc-dc converters. the high oper - ating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and high peak output current supplied by this optocou - pler make it ideally suited for direct driving power mos - fets at high frequency for high efciency conversion. avago r 2 coupler isolation products provide reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial ap - plications. functional diagram truth table led v cc C v ee v out off 0 C 20v low on v uvlo+ high features ? qualifed to aec-q100 grade 1 test guidelines ? automotive temperature range: -40 c to 125 c ? peak output current: 2.0 a min. ? rail-to-rail output voltage ? propagation delay: 110 ns max. ? dead time distortion: +50 ns/-40 ns ? led current input drive with hysteresis ? common mode rejection (cmr): 50 kv/s min. at v cm = 1500 v ? low supply current allow bootstrap half-bridge topology: i cc = 3.9 ma max. ? under voltage lock-out (uvlo) protection with hysteresis for power mosfet ? wide operating v cc range: 10 v to 20 v ? safety approvals: - ul recognized 5000 v rms for 1 min - csa - iec/en/din en 60747-5-5 v iorm = 1140 v peak applications ? hybrid power train dc/dc converter ? ev/phev charger ? automotive isolated mosfet gate drive ? ac and brushless dc motor drives figure 1. acpl-k34t functional diagram note: minimum 1 f bypass capacitor must be connected between pins v cc and v ee . 8 7 6 5 1 2 3 4 anode nc cathode nc vcc v out v ee nc shield
2 ordering information part number option (rohs compliant) package surface mount tape & reel ul 5000 v rms / 1 minute rating iec/en/din en 60747-5-5 quantity acpl-k34t -000e stretched so-8 x x 80 per tube -060e x x x 80 per tube -500e x x x 1000 per reel -560e x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: ACPL-K34T-560E to order product of sso-8 surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval in rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. package outline drawings (stretched so8) recommended pb-free ir profle recommended refow condition as per jedec standard, j-std-020 (latest revision). note: non-halide fux should be used 5.850 0.254 (0.230 0.010) 5 6 7 8 4 3 2 1 dimensions in millimeters and (inches). note: lead coplanarity = 0.1 mm (0.004 inches). floating lead protrusion = 0.25mm (10mils) max. 6.807 0.127 (0.268 0.005) recommended land pattern 12.650 (0.498) 1.905 (0.075) 3.180 0.127 (0.125 0.005) 0.381 0.127 (0.015 0.005) 1.270 (0.050) bsg 7 0.254 0.100 (0.010 0.004) 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 1.590 0.127 (0.063 0.005) 0.450 (0.018) 45 rohs-compliance indicator 0.64 (0.025) 0.200 0.100 (0.008 0.004) part number date code kxxt yww ee extended datecode for lot tracking
3 regulatory information the acpl-k34t is approved by the following organizations: ul ul 1577, component recognition program up to v iso = 5 kv rms csa csa component acceptance notice #5. iec/en/din en 60747-5-5 iec 60747-5-5 en 60747-5-5 din en 60747-5-5 iec/en/din en 60747-5-5 insulation related characteristic (option 060 and 560 only) description symbol option 060 and 560 units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage < 600 v rms for rated mains voltage < 1000 v rms i C iv i C iii climatic classifcation 40/125/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1140 v peak input to output test voltage, method b v iorm 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 2137 v peak input to output test voltage, method a viorm 1.6=vpr, type and sample test with t m =10 sec, partial discharge < 5 pc v pr 1824 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 8000 v peak safety-limiting values C maximum values allowed in the event of a failure, also see figure 5. case temperature input current output power ts i s, input p s,output 175 230 600 c ma mw insulation resistance at ts, v io =500 v rs >10 9 ? insulation and safety related specifcations parameter symbol acpl-k34t units conditions minimum external air gap (clearance) l(101) 8 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detec - tor. tracking resistance (comparative tracking index) cti 175 v din iec 112/vde 0303 part 1 isolation group (din vde0109) iiia material group (din vde 0109)
4 absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 150 c operating temperature t a -40 125 c ic junction temperature t j 150 c 3 average input current i f(avg) 20 ma peak input current (50% duty cycle, < 1 ms pulse width) i f(peak) 40 ma peak transient input current (<1 s pulse width, 300 pps) i f(tran) 1 a reverse input voltage v r 6 v high peak output current i oh(peak) 2.5 a 1 low peak output current i ol(peak) 2.5 a 1 total output supply voltage (v cc - v ee ) 0 25 v output voltage v o(peak) -0.5 v cc v output ic power dissipation p o 500 mw 2 total power dissipation p t 550 mw 3 recommended operating conditions parameter symbol min max. units note operating temperature t a - 40 125 c output supply voltage (v cc - v ee ) 10 20 v input current (on) i f(on) 7 13 ma input voltage (off) v f(off) -5.5 0.8 v electrical specifcations (dc) unless otherwise noted, all minimum/maximum specifcations are at recommended operating conditions. all typical values are at t a = 25 c, v cc - v ee = 10 v, v ee = ground . parameter symbol min. typ. max. units test conditions fig. note high level peak output current i oh -3.5 -2.0 a v cc C v o = 10 v 3 low level peak output current i ol 2.0 4.4 a v o C v ee = 10 v 4 high output transistor rds(on) r ds,oh 2.2 4.0 i oh = -2.0 a 4 low output transistor rds(on) r ds,ol 1.0 2.0 i ol = 2.0 a 4 high level output voltage v oh vccC0.4 vccC0.2 v i f = 10 ma, i o = -100 ma 5, 6 low level output voltage v ol 0.1 0.25 v i o = 100 ma high level supply current i cch 2.5 3.9 ma i f = 10 ma 5 low level supply current i ccl 2.5 3.9 ma v f = 0 v 6 threshold input current low to high i flh 1.5 4.9 ma v o > 5 v 7 threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.25 1.5 1.85 v i f = 10 ma 7 temperature coefcient of input forward voltage d v f / d t a -1.5 mv/ c input reverse breakdown voltage bv r 6 v i r = 100 a input capacitance c in 90 pf f = 1 mhz, v f = 0 v uvlo threshold v uvlo+ 8.1 8.6 9.1 v v o > 5 v, i f = 10 ma 8 v uvlo- 7.1 7.6 8.1 8 uvlo hysteresis uvlo hys 0.5 1.0 v
5 switching specifcations (ac) unless otherwise noted, all minimum/maximum specifcations are at recommended operating conditions. all typical values are at t a = 25 c, v cc - v ee = 10 v, v ee = ground. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 30 60 110 ns v cc = 10 v r g = 4.7 ? , cl = 10 nf, f = 200 khz , duty cycle = 50% v in = 4.5 v C 5.5 v, r in = 350 ? 9,12,14 7 propagation delay time to low output level t phl 30 60 110 ns 10,12,14 pulse width distortion (t phl -t plh ) pwd -40 0 40 ns 11 8 dead time distortion caused by any two parts (t plh -t phl ) dtd -40 50 ns 9 rise time t r 10 30 ns v cc = 10 v, c l = 1 nf, f = 200 khz , duty cycle = 50% v in = 4.5 vC 5.5 v, r in = 350 ? 13, 14 fall time t f 10 30 ns output high level common mode transient immunity |cm h | 50 >75 kv/ s t a = 25 c, v cc = 20 v, v cm =1500 v, with split resistors 15 10, 11 output low level common mode transient immunity |cm l | 50 >75 kv/ s 10, 12 package characteristics unless otherwise noted, all minimum/maximum specifcations are at recommended operating conditions. all typical values are at ta = 25c. parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage* v iso 5000 v rms rh < 50%, t = 1 min, t a = 25 c 13, 14 input-output resistance r i-o 10 14 ? v i-o = 500 v dc 14 input-output capacitance c i-o 0.6 pf f =1 mhz * the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating, refer to your equipment level safety specifcation or avago technologies application note 1074 entitled optocoupler input-output endurance voltage.
6 notes: 1. maximum pulse width = 100 ns, duty cycle = 2%. 2. derate linearly above 110 c free-air temperature at a rate of 13 mw/ c. refer to figure 2 from output ic power dissipation derating chart. 3. total power dissipation is derated linearly above 110 c free-air temperature at a rate of 13 mw/ c. the maximum led and ic junction temperature should not exceed 150 c. 4. output is source at -2.0 a or 2.0 a with a maximum pulse width of 10 s. 5. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 6. maximum pulse width = 1 ms. 7. this load condition approximates the gate load of a 600 v/50 a power mosfet. 8. pulse width distortion (pwd) is defned as t phl -t plh for any given device. 9. dead time distortion (dtd) is defned as t plh C t phl between any two parts under the same test condition. a negative dtd reduces original system dead time; while a positive dtd increases original system dead time. 10. pin 2 and pin 4 must be connected to led common. 11. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state, (i.e., v o > 10 v). 12. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 13. in accordance with ul1577, each optocoupler is proof-tested by applying an insulation test voltage 6000 v rms for 1 second. 14. device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. figure 2. output ic power dissipation derating chart 0 100 200 300 400 500 600 0 25 50 75 100 125 150 175 po p o ? output ic power dissipation ? mw t a ? ambient temperature ? c
7 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 0 1 2 3 4 5 6 7 8 9 1 0 i ol - o u t p u t low c u r r e n t - a 1 2 5 c 2 5 c - 4 0 c 2 2 . 2 2 . 4 2 . 6 2 . 8 3 3 . 2 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 i cch - h i g h l e v e l s u p p l y c u r r e n t - ma v c c = 1 0 v v c c = 1 5 v v c c = 2 0 v 2 2 . 2 2 . 4 2 . 6 2 . 8 3 3 . 2 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 i ccl - l o w l e v e l s u p p l y c u r r e n t - ma v c c = 1 0 v v c c = 1 5 v v c c = 2 0 v 1 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 v f - input forward voltage - f i f l h = 1 0 m a 0 2 4 6 8 1 0 1 2 1 4 1 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 - 4 0 c 2 5 c 1 2 5 c t a - temperature - c t a - temperature - c t a - temperature - c v f - i n p u t f o r w a r d v o l t a g e - v i f - input current - ma v ol - o u t p u t l o w v o l t a g e - v - 4 . 5 - 4 - 3 . 5 - 3 - 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 0 0 . 5 0 1 2 3 4 5 6 7 8 9 1 0 125 c 25 c - 40 c (v cc -v oh ) - h i g h o u t p u t v o l t a g e d r o p - v i oh - output high current - a typical performance plots figure 3. i oh vs. (v cc C v oh ) figure 4. i ol vs. v ol figure 5. i cch vs. temperature figure 6. i ccl vs. temperature figure 7. v f vs. temperature figure 8. i f vs. v f
8 figure 10. t phl vs. temperature figure 11. pwd vs. temperature figure 9. t plh vs. temperature 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 t plh - p r o p a g a t i o n d e l a y - n s t a - temperature - c v i n = 4 . 5 v v i n = 5 v v i n = 5 . 5 v 5 0 5 5 6 0 6 5 7 0 7 5 8 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 v i n = 4 . 5 v v i n = 5 v v i n = 5 . 5 v pwd - p u l s e w i d t h d i s t o r t i o n - ns t phl - p r o p a g a t i o n d e l a y - n s t a - temperature - c t a - temperature - c - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 v i n = 4 . 5 v v i n = 5 v v i n = 5 . 5 v
9 8 7 6 5 1 2 3 4 s h i e l d + _ 1 f v c c = 1 0 v + _ r in = 3 5 0 ? v in = 4 . 5 t o 5 . 5 v 5 0 % d u t y c y c le 2 0 0 k h z r g = 4 . 7 ? c l = 1 0 n f 8 7 6 5 1 2 3 4 s h i e l d + _ 1 f v c c = 1 0 v + _ r in = 3 5 0 ? v in = 4 . 5 t o 5 . 5 v 5 0 % d u t y c y c le 2 0 0 k h z c l = 1 n f t p l h t p h l t r t f 9 0 % 5 0 % 1 0 % v in v o u t 8 7 6 5 1 2 3 4 s h i e l d + _ 1 f v c c = 2 0 v + _ r in 1 21 0 ? 5 v v o r in 2 1 40 ? a b + _ v c m = 1 5 0 0 v 0 . 1 f switch at a: c mh test switch at b: c ml test figure 12. t plh and t phl test circuit figure 13. t r and t f test circuit figure 14. t plh , t phl , t r and t f reference waveforms figure 15. cmr test circuit
10 application information typical high speed mosfet gate drive circuit figure 16. typical high-speed mosfet gate drive circuit anti-cross conduction drive one of the many benefts of using acpl-k34t is the ease to implement anti-cross conduction drive between the high side and low side gate drivers to prevent shoot through event. this safety interlock drive can be realized by interlock - ing the output of bufer u5 and u6 to both high and low side gate drivers, as shown in figure 16. however, due to the propagation delay diference between optocouplers, certain amount of dead time has to be added to ensure sufcient dead time at mosfet gate. refer to dead time and propagation delay section for more details. recommended led drive circuits common mode noise exists whenever there is a diference in the ground level of the optocouplers input control cir - cuitry and output control circuitry. figure 17 and 18 show recommended led drive circuits for high common mode rejection (cmr) performance of the optocoupler gate driver. split limiting resistors are used to balance the impedance at both anode and cathode of the input led for high common mode noise rejection (see figure 15). open drain and open collector drive circuits showed in figure 19 are not recommended. during the of state of the mos - fet/transistor, cathode of the input led sees high impedance and becomes sensitive to noise. in any cases, if designer still prefers to use single mosfet/transistor drive over the recommended cmos bufer drive showed in figure 17 and 18, designer can choose alternative circuits showed in figure 20; however m1/q1 in figure 20 drive circuits will shunt current during led of state, which result in more power consumption. drive power if cmos bufer is used to drive led, it is recommended to connect the cmos bufer at the led cathode. this is because the sinking capability of the nmos is usually more than the driving capability of the pmos in a cmos bufer. drive logic designer can confgure led drive circuits for non-inverting and inverting logic as recommended in figure 17 and 18. external power supply, v dd1 has to be connected to the cmos bufer for the inverting and non-inverting logic to work. if v dd1 supply is lost, led will be permanently of and output will be at low. +5v rin1 rin3 up vdd pha 10v 10u d1 10uf q1 4.7 4.7 +12v 10u q2 10u q3 4.7 4.7 10u q4 d2 rin4 rin2 0.1uf acpl-k34t +hvdc - hvdc u1 u2 u3 u4 pha u5 u6 pha pha led(u1) led(u2) anti-cross conduction drive logic acpl-k34t acpl-k34t acpl-k34t an nc ca nc vcc v out v ee nc an nc ca nc vcc v out v ee nc an nc ca nc vcc v out v ee nc an nc ca nc vcc v out v ee nc
11 figure 19(a) and figure 19(b). not recommended C open drain/open collector drive circuit figure 20(a) and figure 20(b). alternative led drive circuits to replace figure 19(a) and 19(b) bypass and reservoir capacitors supply bypass capacitors are necessary at the input bufer and acpl-k34t output supply pin. a ceramic capacitor with the value of 0.1 f is recommended at the input bufer to provide high frequency bypass, which also helps to improve cmr performance. at the output supply pin (v cc C v ee ), it is recommended to use a 10 f, low esr and low esl capacitor as a charge reservoir to supply instant driving current to mosfet at v out during switching. figure 17. recommended non-inverting drive circuit figure 18. recommended inverting drive circuit figure 19(b) figure 19(a) figure 20(a) figure 20(b) v d d 1 r o v d d 1 1 0 f i s o l a t i o n 0 . 1 f v c c v o u t v e e a n c a v d d 1 r o v d d 1 1 0 f i s o l a t i o n 0 . 1 f v c c v o u t v e e a n c a v d d 1 1 0 f r i n i s o l a t i o n 0 . 1 f v c c v o u t v e e a n c a v d d 1 1 0 f r i n i s o l a t i o n a c p l-k 3 4 t 0 . 1 f a n c a v c c v o u t v e e v d d 1 1 0 f r i n 2 i s o l a t i o n 0 . 1 f r i n 1 v c c v o u t v e e a n c a m 1 v d d 1 1 0 f r i n 2 i s o l a t i o n 0 . 1 f r i n 1 v c c v o u t v e e a n c a q 1 a c p l-k 3 4 t a c p l-k 3 4 t a c p l-k 3 4 t a c p l-k 3 4 t a c p l-k 3 4 t v dd1 = 5 v 10% ratio r in1 : (r in2 +r o ) = 1.5:1 recommended r o +r in1 +r in2 = 350 ? ratio r in1 : (r in2 +r o ) = 1.5:1 v dd1 = 5 v 10% v dd1 = 5 v 10% v dd1 = 5 v 10% r i n 2 r i n 1 r i n 2 r i n 1 recommended r o +r in1 +r in2 = 350 ? ratio r in1 : r in2 = 1.5:1 recommended r in1 +r in2 = 350 ? ratio r in1 : r in2 = 1.5:1 recommended r in1 +r in2 = 350 ?
12 initial power up and uvlo operation insufcient gate voltage to mosfet can increase turn on resistance of mosfet, resulting in large power loss and mos - fet damage due to high heat dissipation. acpl-k34t monitors the output power supply constantly. during initial power up, the acpl-k34t requires maximum 50 s of initial startup time for the internal bias and circuitry to get ready. the gate driver output (v out ) is hold at of state during initial startup time. thereafter, when the output power supply is lower than under voltage lockout (v uvlo- ) threshold, gate driver output will shut of to protect mosfet from low voltage bias. when the output power supply is more than the v uvlo+ threshold, v out is released from low state and it follows the input led drive signal, as shown in figure 21. figure 21. acpl-k34t initial power-up and uvlo operation figure 22a. negative dtd reduces original dt dead time distortion and propagation delay dead time is the period of time during which both high side and low side power transistors (shown as q1 and q2 in fig - ure 16) are of. any overlap in q1 and q2 conduction will result in a shoot-through event and large short circuit current will fow through the power devices between the high side and low side power rail. acpl-k34t includes a dead time distortion (dtd) specifcation intended to help designers optimize dead time in a power inverter design. a negative dtd value will decrease the system dead time, and so a negative dtd must be com - pensated by adding extra dead time to the design. figure 22a shows that dead time after optocoupler is reduced by negative dtd. on the other hand, a positive dtd will add to the system original dead time, and so a positive dtd will cause dead time redundancy to the system. figure 22b shows that dead time after optocoupler is increased by positive dtd. v c c v i n ( l e d ) v o u t i n i t i a l s t a r t u p t i m e v u v l o - v u v l o + v u v l o + figure 22b. positive dtd increased original dt figure 22. dead time and propagation delay waveforms
13 to prevent cross-conduction between high side and low side power transistors, minimum dead time (dt min) must be introduced to the system. for example, given dtd min = -40 ns and dtd max = 50 ns, if designers target to have minimum dead time (dt min) of 20 ns after the optocoupler, then initial dead time (dt) needed for the system can be calculated as: dt = dt min C dtd min = 20ns C (-40ns) = 60ns maximum dead time (dt max) after the optocoupler can be calculated as: dt max = dt + dtd max = 60 ns + 50 ns = 110 ns by introducing dt = 60 ns, the overall system dead time can vary from 20 ns to 110 ns due to the optocouplers dtd. note: the propagation delays used to calculate dead time distortion (dtd) are taken at equal temperatures and test conditions since the optocouplers used are typically mounted close to each other and are switching the same type of mosfets.
14 thermal resistance model for acpl-k34t the diagram for measurement is shown in figure 23. here, one die is heated frst and the temperatures of all the dice are recorded after thermal equilibrium is reached. then, the second die is heated and all the dice temperatures are recorded. with the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. the thermal resistance calculation can be cast in matrix form. this yields a 2 by 2 matrix for our case of two heat sources. r 11 r 12 p 1 = ? t1 r 21 r 22 p 2 ? t2 figure 23. diagram of acpl-k34t for measurement r11: thermal resistance of die1 due to heating of die1 ( c/w) r12: thermal resistance of die1 due to heating of die2 ( c/w) r21: thermal resistance of die2 due to heating of die1 ( c/w) r22: thermal resistance of die2 due to heating of die2 ( c/w) p1: power dissipation of die1 (w) p2: power dissipation of die2 (w) t1: junction temperature of die1 due to heat from all dice ( c) t2: junction temperature of die2 due to heat from all dice ( c) t a : ambient temperature (?c) ?t1: temperature diference between die1 junction and ambient (?c) ?t2: temperature deference between die2 junction and ambient ( c) t1 = (r11 p1 + r12 p2) + t a ------------------(1) t2 = (r21 p1 + r22 p2) + t a ------------------(2) measurement is done on both low and high conductivity boards as shown below: layout measurement data low conductivity board: r11=191 ?c/w r12=r21= 68.5?c/w r22=77?c/w high conductivity board: r11=155 ?c/w r12=r21= 64?c/w r22=41?c/w note that the above thermal resistance r11, r12, r21 and r22 can be improved by increasing the ground plane/copper area. 1 2 3 4 8 7 6 5 d ie 1 : l e d d ie 2 : d e t e c t o r 76mm 79mm
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, the a logo, and r 2 coupler are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-4229en - september 16, 2013 application and environment design for acpl-k34t needs to ensure that the junction temperature of the internal ic and led within the gate drive optocoupler do not exceed 150 c. the equation (1) and (2) provided above are for the purposes of estimating the junction temperatures. for example: calculation of led and output ic power dissipation led power dissipation, p e = i f(led) (recommended max) * v f(led) (at 125 c) * duty cycle = 13 ma * 1.25 v * 50% = 8.125 mw output ic power dissipation, p o = v cc (recommended max) * i cc (max) + p hs + p ls = 20 v * 4 ma + 53.3 mw + 32 mw = 165.3 mw where phs = high side switching power dissipation = (v cc * q g * f pwm )* r ds,oh(max) / (r ds,oh(max) + r gh ) /2 = (20 v * 80nc * 200 khz) * 4 ? /(4 ? +8 ? )/2 = 53.3mw pls = low side switching power dissipation = (v cc * q g * f pwm )* r ds,ol(max) / (r ds,ol(max) + r gl ) /2 = (20 v * 80 nc * 200 khz) * 2 ? /(2 ? +8 ? )/2 = 32 mw q g = gate charge at supply voltage f pwm = led switching frequency r gh = gate charging resistance r gl = gate discharging resistance calculation of led junction temperature and output ic junction temperature at ta=125 c: led junction temperature, t1 = (r11 p e + r12 p o ) + t a = (191 c/w * 8.125 mw + 68.5 c/w * 165.3 mw) + 125 c = 138 c < t j (absolute max) of 150 c output ic junction temperature, t2 = (r21 p e + r22 p o ) + t a = (68.5 c/w * 8.125 mw + 77 c/w * 165.3 mw) + 125 c = 138 c < t j (absolute max) of 150 c

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